The present invention relates to a semiconductor device and an electronic device, and mainly to a semiconductor device having a BGA (Ball Grid Array) structure and a technology effective for application to a power supply technique of an electronic device equipped with the semiconductor device.
It has been reported that Unexamined Patent Publication No. Hei 9(1997)-22977 (hereinafter called Reference 1) and Unexamined Patent Publication No. Hei 11(1999)-324886 (hereinafter called Reference 2) exist as ones considered to be those related to the invention of the present application as a result of investigations of the known examples subsequent to the completion of the invention of the present application. Reference 1 has proposed a BGA structure wherein signal pads, ground pads and power pads are alternately disposed and wires are made substantially parallel and approximately identical in length to thereby reduce noise or the like. Power and ground wires are intensively provided between internal and external terminals to thereby reduce the number of the external terminals. In Reference 2, rewiring layers are used on a chip to form plane layers, and the plane layers are used to unify wirings, thereby reducing the number of flip-chip bumps on the semiconductor chip.
As a technology of reducing external power terminals with respect to power supply electrodes provided for the semiconductor chip, there is known a technology of a bus bar comprised of a lead frame used in a DRAM or the like. In the bus bar technology, a plurality of power supply pads are provided for a semiconductor chip and respectively bonded onto one lead frame by bonding wires to thereby reduce the number of the external power terminals. Namely, the lead frame is used as part of power wirings.
A semiconductor device needs relatively large current drive capability to drive, at high speed, a load such as relatively large parasitic capacitance added to its corresponding output terminal when a printed circuit board is equipped with the semiconductor device. It is known that when an output circuit for causing such a large current to flow is provided, large noise is produced in a power terminal of the output circuit. In order to reduce the occurrence of such large noise, there is a need to suppress power impedance as low as practicable. In order to avoid the transfer of the power noise produced in the output circuit to other circuits, a power supply line of the output circuit and power supply lines for an input circuit and an internal circuit are separated from one another on a semiconductor chip, and power pads are provided in association with their lines.
A package having a BGA structure can be provided with a large number of external terminals. Particular awareness of a problem about the assignment of external terminals in a one-to-one correspondence with power supply pads provided for the semiconductor chip was not in existence. If mentioned in reverse, the external terminals are respectively assigned in the one-to-one correspondence with the power supply pads provided for the semiconductor chip, so that preference is given to the fact that voltages are transferred to the power supply pads of the semiconductor chip from the printed circuit board via the external terminals, a parasitic inductance component that contributes to the occurrence of the noise, is greatly reduced to thereby suppress the occurrence of the noise, and in addition noise from the output circuit side is prevented from being transferred to the internal circuit and the input circuit.
When considered in terms of the power noise, for example, the parasitic inductance increases in reverse although the above technology using the bus bar is capable of reducing the number of external terminals. In a package of a DRAM, an inductance component of a bonding wire is about 1 nH. On the other hand, an inductance component of a lead frame is about 4 nH. Assuming that five ground pads exist in the semiconductor chip with respect to one bus bar, for example, the combined inductance at the bonding wire portion can be reduced to ⅕ nH but the inductance of the lead frame 4 nH exists as it is because one lead frame is commonly used. Therefore, the total inductance is not improved like ⅕+4=4.2 nH. On the other hand, when a lead and an external terminal are provided in a one-to-one correspondence with each ground pad of the semiconductor chip, the inductance can be reduced like (1+4)/5=1 nH.
With advances in micro-fabrication of a device, however, the scale of a circuit formed on one semiconductor chip increases and correspondingly the number of external terminals has a tendency to increase. The increase in the number of the external terminals becomes insignificant so far owing to the micro-fabrication or the like of the device on the semiconductor chip side. However, a package substrate equipped therewith needs to use one large in size in association with the increase in the number of the external terminals, so that the cost of the package substrate increases and the size of a semiconductor device per se also increases, thus causing a problem that becomes the factor that interferes with downsizing of an electronic device. References 1 and 2 referred to above perfectly lack consideration for a parasitic inductance component in a power supply path and consideration for noise produced in the output circuit. They do not show any suggestion for solving the problem about the power noise.
An object of the present invention is to provide a semiconductor device which reduces the number of external power terminals while suppressing power noise. Another object of the present invention is to provide a semiconductor device which realize its scale down while suppressing power noise. A further object of the present invention is to provide an electronic device efficiently equipped with a bypass condenser. The above, other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
A summary of a typical one of the inventions disclosed in the present application will be described in brief as follows: A package substrate is provided which is equipped, on its surface, with a semiconductor chip having a plurality of output circuits each outputting a signal formed by an internal circuit, a first voltage supply electrode which supplies an operating voltage to the internal circuit, and a plurality of second voltage supply electrodes which supply operating voltages to the plurality of output circuits, and which is provided on its back surface, external terminals and has a plurality of wiring layers, and a first electrode having one end connected to the first voltage supply electrode of the semiconductor chip, a plurality of second electrodes having one ends respectively connected to the plurality of second voltage supply electrodes, first wiring means which includes a wiring layer different from the surface wiring layers and commonly connects the second electrodes respectively, second wiring means which connects the first electrode and a corresponding one of the external terminals provided on the back surface, and a plurality of third wiring means which respectively connect the first wiring means and a plurality of external terminals equivalent to a number aggregated to a number fewer than the second electrodes provided on the back surface are provided on the surface of the package substrate.
A summary of another typical one of the inventions disclosed in the present application will be described in brief as follows: A printed circuit board is provided which is equipped, on its surface, with a semiconductor device having a plurality of power terminals which supply operating voltages, and a plurality of ground terminals each of which supplies a circuit ground potential, and which is provided with a bypass condenser on its back surface, and a plurality of first electrodes having one ends respectively connected to the plurality of power terminals of the semiconductor device, a plurality of second electrodes having one ends respectively connected to the plurality of ground terminals of the semiconductor device, first wiring means which includes a wiring layer different from a wiring layer formed with the first electrodes and commonly connects the first electrodes, second wiring means which commonly connects the second electrodes, third wiring means which connects the first wiring means and third electrodes equivalent to a number aggregated to a number fewer than the first electrodes provided on the back surface, fourth wiring means which connects fourth electrodes equivalent to a number aggregated to a number fewer than the second electrodes, and a bypass condenser provided between each of the third electrodes and each of the fourth electrode are provided on the surface of the printed circuit board.
There is provided an electronic device comprising a semiconductor device, and a printed circuit board equipped with the semiconductor device mounted on its surface and provided with a bypass condenser on its back surface, wherein the semiconductor device includes a plurality of power terminals which supply operating voltages, and a plurality of ground terminals each of which supplies a circuit ground potential, and wherein the printed circuit board includes a plurality of first electrodes provided on a substrate surface equipped with the semiconductor device and having one ends respectively connected to the plurality of power terminals of the semiconductor device, a plurality of second electrodes provided on the substrate surface equipped with the semiconductor device and having one ends respectively connected to the plurality of ground terminals of the semiconductor device, first wiring means which includes a wiring layer different from a wiring layer formed with the first electrodes and commonly connects the first electrodes, second wiring means which includes a wiring layer different from a wiring layer formed with the second electrodes and commonly connects the second electrodes, third wiring means which connects the first wiring means and third electrodes equivalent to a number aggregated to a number fewer than the first electrodes provided on the back surface, fourth wiring means which connects the second wiring means and fourth electrodes equivalent to a number aggregated to a number fewer than the second electrodes provided on the back surface, and a bypass condenser provided between each of the third electrodes and each of the fourth electrode.
According to the electronic device, the semiconductor device includes external terminals each of which is of a grid array type.